How to set up the ZCU106 evaluation board and run the TRD.This tutorial contains information about: SDI-Tx display pipeline implemented in the PL.HDMI-Tx display pipeline implemented in the PL.SDI-Rx capture pipeline implemented in the PL.File source (SD card, USB storage, SATA hard disk).MIPI CSI-2 Rx capture pipeline implemented in the PL.HDMI-Rx capture pipeline implemented in the PL.Test pattern generator (TPG) implemented in the PL.The TRD supports the following video interfaces: The TRD consists of four design-modules described in section 4.1. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design.

The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The remaining blocks are common to all design modules as shown. The components of each design module are highlighted in unique colors in the diagram.

It consists of four Design Modules (DM1, DM2, DM3, DM4).

The below figure shows the TRD block diagram. Overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS).

Frame-drops fixed in 4Kp60 AVC pipeline till 60 Mbps.

Updated all projects, IPs, and tools versions to 2018.2.

This wiki page complements the 2018.2 version of the VCU TRD.

Xilinx vivado download 2018.2